Normally, necessary instructions and data to be used by a processor are stored in a shared storage of a multiprocessor system, Each of the processor modules frequently accesses the shared storage. In this connection, exclusive instructions are indispensable for accesses to a shared storage, and among them is a CSI (compare and store interlocked) instruction for substituting or rewriting data when it is determined that data read from a shared storage coincides with the data expected by software. However, when a CSI instruction is executed, an exclusive control is performed such that a system bus between a processor module and a shared storage module is exclusively occupied until the end of the instruction. During the execution of the CSI instruction, no other processor modules are permitted to access the system bus, thereby greatly reducing the system performance. Therefore, it is requested that the range of the exclusive control and the time taken for it to execute a CSI instruction are limited to the least possible extent.
As shown in FIG. 20, a conventional multiprocessor system forms a computer system referred to as a multiprocessor system in which a plurality of processor modules 10 and a plurality of shared storage modules 12 are connected through a system bus 16 for transmitting data.
Thus, exclusive instructions are required to access a shared storage in a multiprocessor system, and a CSI instruction is one of them.
As shown in FIG. 21, the operation sequence of a CSI instruction is fixed such that, when the data of a certain address at which the shared storage comprising a plurality of shared storage modules (SSM) 12 is located are to be rewritten, access address data can be read and actually rewritten if the read data coincides with the data anticipated by a central processing unit (.mu.P) 18 of the processor module 10 to be stored at the access address.
After the access address data are read, the CSI instruction performs exclusive control so that another central processing unit 18 in other processor modules 10 cannot access and update the access address while the comparison results in coincidence and the address data are rewritten.